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CUDA-x86.

REAL*16 implementation?
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mkcolg



Joined: 30 Jun 2004
Posts: 5952
Location: The Portland Group Inc.

PostPosted: Fri Mar 11, 2005 9:13 am    Post subject: Reply with quote

Hi Johnix,

The AMD XMM floating point registers and instructions are 128-bit. However, the floating point data types are still only 32 and 64-bits (Section 4.4.6 of the AMD Architecture Guide). This means you can perform up to four simultaneous single-precision (32-bit) floating point calculations or two double precision (64-bit) floating point calculations when using vector or "packed" instructions. Using the "-Mvect=sse" optimization, which is part of the aggregate flag "-fastsse", tells the compiler to generate these vector instructions.

Hope this helps,
Mat
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