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Used of shared memory in device function
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DAVID-SPH



Joined: 23 May 2011
Posts: 28

PostPosted: Thu Aug 23, 2012 5:18 am    Post subject: Reply with quote

Any other bit intrinsics not supported?... I kind of need to know because I'm programming a Radix Sort on CUDA Fortran and I will make heavy use of all of them.

Best Regards,
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mkcolg



Joined: 30 Jun 2004
Posts: 6211
Location: The Portland Group Inc.

PostPosted: Thu Aug 23, 2012 10:47 am    Post subject: Reply with quote

It will be the same for all of them (btest, iand, ibclr, ibits, ibset, ieor, ior, ishft, ishftc, not) since we don't have the GPU run time device routine. If the intrinsic gets inlined, then it's not a problem.

- Mat
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DAVID-SPH



Joined: 23 May 2011
Posts: 28

PostPosted: Thu Aug 23, 2012 5:10 pm    Post subject: Reply with quote

mmm can I use the "inline" keyword to force it to be inlined?
the ibits one is critical for the radix sort...
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mkcolg



Joined: 30 Jun 2004
Posts: 6211
Location: The Portland Group Inc.

PostPosted: Fri Aug 24, 2012 10:01 am    Post subject: Reply with quote

Quote:
mmm can I use the "inline" keyword to force it to be inlined?
the ibits one is critical for the radix sort...
When they can be inlined, they are inlined. But the user can't effect this.

I wish I knew off hand the exact circumstance of when each are inlined or not. Though, I'll do some digging on ibits and get back to you.

- Mat
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mkcolg



Joined: 30 Jun 2004
Posts: 6211
Location: The Portland Group Inc.

PostPosted: Tue Sep 04, 2012 1:30 pm    Post subject: Reply with quote

Word from engineering is that they'll have "btest", "iand", "ibclr", "ibset", "ieor", and "iand" into 12.9. Granted, I haven't verified it myself, but that's the word.

- Mat
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