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CUDA-x86.

Bit field width restriction to 32 bits

 
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cdk



Joined: 01 Jun 2005
Posts: 1

PostPosted: Wed Jun 01, 2005 10:31 am    Post subject: Bit field width restriction to 32 bits Reply with quote

According to the PGI user guide, there is a restriction on the width of bitfields in structures to 32 bits. I am porting a code that frequently uses fields wider than this with a container class of 'long' or 'long long' to achieve a potential width of 64 bits. This is an important performance/storage issue for this code. I'm curious why this restriction is present as it does not appear in other compilers I'm familiar with.

Cheers,
Chris
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mkcolg



Joined: 30 Jun 2004
Posts: 5952
Location: The Portland Group Inc.

PostPosted: Wed Jun 01, 2005 12:13 pm    Post subject: Reply with quote

Hi Chris,

The other compilers have added a language extension to allow for 'wide' bit-fields. While we are considering adding this extension in a future release, we currently only use the ANSI C standard definition which states that bit-fields must be an int or bool.

Thanks,
Mat
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