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CUDA-x86.

compilation of mpich 3.0.1 fails with on 32-bit machines
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mkcolg



Joined: 30 Jun 2004
Posts: 5952
Location: The Portland Group Inc.

PostPosted: Fri Jan 18, 2013 11:13 am    Post subject: Reply with quote

Thanks Andy, "-fpic" was the missing piece and I've now been able to recreate the error.

The problem is with the asm statement at line 69 of "include/private/cpuid.h". I'm looking into if this asm isn't valid for use with fPIC or if we're doing something wrong. In either case, we shouldn't be issuing an internal compiler error.

Quote:
I'm not sure why you don't see the same behaviour.
I'm not sure. Either -fpic wasn't being added (I didn't explicitly request shared libraries, but nether did you) or my configuration by-passed this asm statement. I'll need to see what define flags make used.

- Mat
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mkcolg



Joined: 30 Jun 2004
Posts: 5952
Location: The Portland Group Inc.

PostPosted: Fri Jan 18, 2013 3:50 pm    Post subject: Reply with quote

Hi Andy,

Here's the response from the compiler engineer that I ask to look at this:

Quote:
The extended asm fails because we have one less general purpose register
to work with when we compile with -fpic on 32-bit. Compiling with -fpic
on 32-bit removes %ebx from the pool of general purpose registers
because it uses %ebx for the PIC register. The 64-bit compilers do not
have this issue because the ABI provides a dedicated PIC register. We
will investigate this further to see if we can improve the register
usage of this asm statement.

Also the programmer is using a hard coded %ebx in their asm statement.
All hard coded registers in an asm statement must be included in the asm
statement's clobber list. Otherwise, the asm statement may clobber a
value in a hard coded register that the compiler is using for something
else. For example, note the addition of "%ebx" in the clobber list below
(the last part of the asm statement):

asm(
"mov %%ebx,%2\n\t"
"cpuid\n\t"
"xchg %2,%%ebx\n\t"
"movl %k2,%1\n\t"
: "+a" (*eax), "=m" (*ebx), "=&r"(sav_ebx),
"+c" (*ecx), "=&d" (*edx) ::
"%ebx" );


As a work around, the programmer can either compile without -fpic on 32-bit, or possibly use fewer registers in their asm statement.


I add a problem report (TPR#19078) to see if improvements can be done or better error detection can be give. In any case, the compiler shouldn't give an ICE.

Thanks,
Mat
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p.j.knowles



Joined: 20 Apr 2006
Posts: 17

PostPosted: Wed Jan 30, 2013 7:23 am    Post subject: Reply with quote

Mat,

Thanks for the info - I've only just noticed your response since I didn't realize the thread had gone onto a second page.

I implemented a workaround which forces the mpich configure to fail when testing for -fpic compiler flag:

Code:
for i in `find . -name configure`; do sed -i -e 's/-fpic/-fpic-fail/' ${i}; done


The good news is that the newly released pgcc 13.1 does not have such a problem compiling mpich, so it appears this problem has been fixed.

Thanks,

Andy
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mkcolg



Joined: 30 Jun 2004
Posts: 5952
Location: The Portland Group Inc.

PostPosted: Wed Jan 30, 2013 10:26 am    Post subject: Reply with quote

Quote:
The good news is that the newly released pgcc 13.1 does not have such a problem compiling mpich, so it appears this problem has been fixed.
I'm a bit surprised by that since I don't see any updates to TPR#19078 and the report came too late to be included in 13.1. We may have found the issue internally or just got lucky.

- Mat
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MCS Systems



Joined: 19 Jun 2013
Posts: 1

PostPosted: Fri Feb 07, 2014 3:26 pm    Post subject: Reply with quote

Quote:
The good news is that the newly released pgcc 13.1 does not have such a problem compiling mpich, so it appears this problem has been fixed.


I still see this issue using pgcc 13.6 on 32-bit systems. I can replicate it when compiling hwloc standalone or with mpich.
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