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karim
Joined: 17 Aug 2004 Posts: 2
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Posted: Tue Aug 17, 2004 7:45 am Post subject: scalapack and quadruple precision |
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Hello
Is it possible to compile SCALAPACK in quadruple precision using the PG compiler ?
Thanks
Karim. |
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paulv
Joined: 26 Jul 2004 Posts: 19 Location: JCSDA
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Posted: Tue Aug 17, 2004 11:53 am Post subject: |
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Hello,
As far as I can tell, pgf90 v5.2-1 doesn't support quad precision. The result of my Test_Type_Kinds program for PGI on a linux x86 system is:
Kind types:
Double float kind type: 8
Quad float kind type: 8
(If the Quad kind type doesn't exist, i.e. = -1, then my code defaults to the next "largest" type, in this case the Double float kind which == 8.)
Using Lahey v6.2 shows that quad precision is available on x86,
Kind types:
Double float kind type: 8
Quad float kind type: 16
but my experience has been that, when available, Quad precision is extremely slow since the calcs aren't done in hardware, but in software. But, I know nothing about SCALAPACK or your hardware, so my observations may not apply.
cheers,
paulv |
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mkcolg
Joined: 30 Jun 2004 Posts: 4996 Location: The Portland Group Inc.
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Posted: Tue Aug 17, 2004 2:31 pm Post subject: Quad not supported |
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Hi Karim,
PGI does not support quad precision because of the lack of hardware support. As Paulv points out, software support of real*16 would have very poor performance.
Thanks for the question.
Mat |
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karim
Joined: 17 Aug 2004 Posts: 2
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Posted: Thu Aug 19, 2004 12:51 am Post subject: |
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Hi
Thanks for your answers,
For the problem of performance with quad precision, I though to use opteron processors.
Cheers
Karim. |
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mwolfe
Joined: 13 Jul 2004 Posts: 20
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Posted: Thu Aug 19, 2004 4:31 pm Post subject: |
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Hi Karim
Opteron extends the x86 processor by enlarging the integer registers from 32bit to 64bits, adding 8 new 64bit integer registers, and adding 8 new SSE registers. However, it does not have hardware support for 128bit floating bit arithmetic. The 128bit SSE registers are used in four modes:
- single 32bit floating point, ignoring the other 96 bits (SSE1)
- packed 4x32bit floating point, using all 128 bits (SSE1)
- single 64bit floating point, ignore the other 64 bits (SSE2)
- packed 2x64bit floating point, using all 128 bits (SSE2)
None of the x86 processors have hardware for 128bit floating point arithmetic.
I'm not sure any mainstream microprocessor does.
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